ADC linearity improvement
US6847320B1 · kind B1 · utility
9Cited by
3References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2004 |
| Grant date | Jan 25, 2005 |
| Priority date | — |
| Expiry date | Mar 30, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/368
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and circuit for improving linearity of a folding or flash analog-digital-converter (ADC) circuit. Averaging resistors connect outputs of each of a bank of first pre-amplifiers. A series adjustment resistor is placed between each node connecting the output of a first bank pre-amplifier and the associated averaging resistor, and the input of each of a second bank pre-amplifier. An adjustment current is injected through the adjustment resistor during a calibration. A permanent value for adjustment current is determined such that an effect of offset errors is substantially minimized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.