Method of controlling data reading capable of increasing data transfer rate in SDRAM of the posted CAS standard
US6847580B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2002 |
| Grant date | Jan 25, 2005 |
| Priority date | — |
| Expiry date | Feb 21, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4087
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for controlling reading data that can increase the data transfer rate in an SDRAM of a posted CAS standard. A memory cell array is constituted by two sub-arrays that can be independently activated. When a READ command is received as an input one clock cycle after the input of an ACTV command, a row decoder activates only the sub-array containing the memory cell that is selected by a row address AX and column address AY, and then carries out the operations for reading data. The present invention thus reduces the areas that must be activated, thereby decreasing the load on the power supply and, when amplifying bit lines, shortening the time for the voltage of bit lines to attain the stipulated voltage. Consequently, the present invention increases the speed of reading data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.