Ultra-high linearity RF passive mixer
US6847808B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 28, 2002 |
| Grant date | Jan 25, 2005 |
| Priority date | — |
| Expiry date | Feb 14, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D2200/0088
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A CMOS implemented passive mixer circuit for improving linearity performance in wireless communication systems is described, including dual pairs of NMOS FETs and dual pairs of PMOS FETs. Each NMOS FET is connected in parallel with a corresponding PMOS FET. A local oscillator signal is provided to the gate of one FET while a 180-degree phase shifted local oscillator signal is provided to the gate of its complementary FET. Because the complementary FETs are driven by local oscillator signals that are 180 degrees out of phase, the NMOS FET is turned on for at least a portion of the positive cycle of the local oscillator signal and the PMOS FET is turned on for at least a portion of the negative cycle of the 180-degree phase shifted local oscillator signal. Distortion in the mixed output signal is thereby reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.