Method and apparatus for faster block size calculations for interleaving
US6848036B1 · kind B1 · utility
3Cited by
1References
3Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 23, 2000 |
| Grant date | Jan 25, 2005 |
| Priority date | — |
| Expiry date | Sep 19, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/2703
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An interleaver for any modem or transmitter which transmits digital data. The interleaver eliminates the iterative divide step of a first prior art method to calculate the final depth of each block and the divide followed by a multiply step of a second prior art method. This is done by calculating the minimum depth, i.e., number of rows, for each 2-D block of data using a divide step and retaining the remainder. The remainder is used to determine how many blocks get an extra row when the burst length and width of each row precludes all blocks from having the same number of rows.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.