Optimal redundant arithmetic for microprocessors design
US6848043B1 · kind B1 · utility
5Cited by
13References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2000 |
| Grant date | Jan 25, 2005 |
| Priority date | — |
| Expiry date | Apr 27, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3838
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for improving system performance using redundant arithmetic are disclosed. In one embodiment, one or more dependency chains are formed. A dependency chain may comprise of two or more instructions. A first instruction may generate a result in a redundant form. A second instruction may accept the result from the first instruction as a first input operand. The instructions in the dependency chain may execute separately from instructions not in the dependency chain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.