System and method for scrubbing errors in very large memories
US6848063B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2001 |
| Grant date | Jan 25, 2005 |
| Priority date | — |
| Expiry date | Apr 25, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/106
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for improving scrubbing techniques are provided. In one aspect, the error correction code for a memory line is strengthened by reorganizing the memory line into distinct portions and providing an error code set that includes a distinct error code for each portion of the memory line. In another aspect of the invention, the scan rate is effectively increased by moving memory scrubbing functionality into the memory system and distributing it among a number of subcomponents that can operate scrubbing functions in parallel. The effective scan rate increase reduces the probability of failure for any given ECC strength.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.