Patent · US Expired

Method and apparatus for verification of memories at multiple abstraction levels

US6848084B1 · kind B1 · utility

8Cited by

18References

66Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Manish Pandey · San Jose, US
Mitchell Hines · San Jose, US
Chih-Chang Lin · San Jose, US

Key dates

Filing date	Dec 20, 2002
Grant date	Jan 25, 2005
Priority date	—
Expiry date	Dec 20, 2022

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/33
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

This invention relates to method and apparatus for verification of circuit designs containing memories. At a register transfer abstraction level, verification of a circuit design requires showing that the register transfer language (RTL) abstraction of the design is logically equivalent to the design implementation represented at the logic (e.g., gate and/or flip-flop) and/or the transistor (e.g. implementation verification) abstraction levels, as well as logic simulation of the design RTL embedded in a system-level test bench for verification at the system-abstraction level.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.