Method and apparatus for performing technology mapping

US6848086B2 · kind B2 · utility

Assignee

• Cadence Design Systems, Inc. · US

Inventors

• Steven Teig · Menlo Park, US
• Asmus Hetzel · Berlin, DE

Key dates

• Filing date: Jan 31, 2002
• Grant date: Jan 25, 2005
• Expiry date: Feb 8, 2022

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F30/327
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Some embodiments of the invention provide a method for pre-tabulating sub-networks. This method (1) generates a sub-network that performs a function, (2) generates a parameter based on this function, and (3) stores the sub-network in a storage structure based on the generated parameter. In some embodiments, the generated sub-network has several circuit elements. Also, in some embodiments, the generated sub-network performs a set of two or more functions. Some embodiments store each generated sub-network in an encoded manner. Some embodiments provide a method for producing a circuit description of a design. This method (1) selects a candidate sub-network from the design, (2) identifies an output function performed by the sub-network, (3) based on the identified output function, identifies a replacement sub-network from a storage structure that stores replacement sub-networks, and (4) replaces the selected candidate sub-network with the identified replacement sub-network in certain conditions. In some embodiments, this method is performed to map a design to a particular technology library. Some embodiments provide a data storage structure that stores a plurality of sub-networks based…