Physically defined varactor in a CMOS process
US6849488B2 · kind B2 · utility
1Cited by
1References
16Claims
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Key dates
| Filing date | May 24, 2004 |
| Grant date | Feb 1, 2005 |
| Priority date | — |
| Expiry date | May 24, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0685
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A differential varactor is physically defined in a CMOS process using a using the diffusion mask of a polycide gate rather than a P (+) mask, as is commonly used. The differential CMOS varactor may be used in a a phase locked loop (PLL) of a voltage-controlled oscillator (VCO) to enable a transceiver to communicate at OC-3/STM-1 data rates using SONET/SDH signaling formats.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.