Method for manufacturing a nonvolatile memory device including an opening formed into an inverse-tapered shape
US6849500B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2003 |
| Grant date | Feb 1, 2005 |
| Priority date | — |
| Expiry date | Feb 28, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method, for manufacturing a nonvolatile memory device, includes: forming a first insulating layer above a semiconductor layer; forming a first conductive layer above the first insulating layer: forming a stopper layer above the first conductive layer; patterning the stopper layer and the first conductive layer; forming an ONO film made of a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer above the semiconductor layer and on both side surfaces of the first conductive layer; forming a second conductive layer above the ONO film; applying anisotropic etching to the second conductive layer, and thereby forming a side wall-like control gate aside each of both side surfaces of the first conductive layer, the ONO film being interposed therebetween; forming an impurity layer to be a source region or a drain region inside of the semiconductor layer; forming a second insulating layer over an entire surface; polishing the second insulating layer so as to expose the stopper layer; removing the stopper layer; forming, on the entire surface, a third conductive layer made of a laminate film of a titanium layer and a titanium nitride layer; patterning the third…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.