Low temperature sinterable dielectric ceramic composition and multilayer ceramic chip capacitor using the same
US6849567B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2003 |
| Grant date | Feb 1, 2005 |
| Priority date | — |
| Expiry date | Jul 29, 2023 |
Classification
- Technology area (CPC C)Chemistry; Metallurgy
- CPC primaryC04B2237/704
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A low temperature sinterable dielectric ceramic composition and a multilayer ceramic chip capacitor. The dielectric ceramic composition is expressed by the general formula: aBaTiO3-bMgCO3-cY2O3-dCr2O3-eV2O5-f(xZrO2-y(K,Li)2O-zSiO2) (x+y+z=1; 0.05≦x≦0.18, 0.01≦y≦0.08, and 0.7.4≦z≦0.93); in which a, b, c, d, e and f are molar ratios; a=100, 1.0≦b≦2.0, 0.2≦c≦2.0, 0.02≦d≦0.3, 0.02≦e≦0.3, and 0.5≦f<2. The multilayer ceramic chip capacitor is prepared using the dielectric ceramic composition. The dielectric composition according to the present invention can be sintered at a low temperature without decrease of a dielectric constant, making it possible to make ultra thin-layered dielectrics.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.