SRAM self-timed write stress test mode
US6850075B1 · kind B1 · utility
0Cited by
8References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2000 |
| Grant date | Feb 1, 2005 |
| Priority date | — |
| Expiry date | May 8, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0403
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a test circuit that may be configured to generate a test signal having a predetermined pulse width in response to a control input. The test signal may track process corners of the integrated circuit and may be used to predict a failure of the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.