Level shifter
US6850090B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 27, 2003 |
| Grant date | Feb 1, 2005 |
| Priority date | — |
| Expiry date | Oct 27, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/017
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Provided is a level shifter including: a first level shifter circuit having first and second transistors whose sources are applied with a power source voltage and drains are connected with gates of the other transistors, and third and fourth transistors whose gates are applied with input and inverted signals, drains are connected with the drains of the first and second transistors, and sources are grounded; and a second level shifter circuit having fifth and sixth transistors whose sources are grounded and drains are connected with gates of the other transistors, and seventh and eighth transistors whose sources are applied with the power source voltage, gates are applied with the input and inverted signals, and drains are connected with the drains of the fifth and sixth transistors, the drains of the first and fifth transistors and the drains of the second and eighth transistors being connected with each other, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.