Accurate, high drive, zero offset voltage buffer
US6850116B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 27, 2002 |
| Grant date | Feb 1, 2005 |
| Priority date | — |
| Expiry date | Nov 27, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/331
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A low offset voltage buffer which comprises a first, second, third and fourth MOS device, each comprising a gate, a source and a drain; a current source coupled to the drains of the first and second MOS devices; a current sink coupled to the sources of the third and fourth MOS devices; an input coupled to the gate of the third MOS device and an output coupled to the source of the first MOS device. The source of the first MOS device is coupled to the drain of the third MOS device and the source of the second MOS device is coupled to the drain of the fourth MOS device. The voltage buffer can also be implemented in both NMOS and PMOS devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.