CMOS transceiver having an integrated power amplifier
US6850117B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2003 |
| Grant date | Feb 1, 2005 |
| Priority date | — |
| Expiry date | Jan 7, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/724
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a breakdown resistant transistor structure for amplifying communication signals. This structure includes a first NMOS transistor having a source connected to ground and a first gate for receiving the input radio frequency signal. The first gate is disposed above a first insulator and the first NMOS transistor having a first transconductance and a first breakdown voltage associated therewith. Also included is a second NMOS transistor having a source connected to the drain of the first NMOS transistor, a gate connected to the reference DC voltage, and a drain that provides the output for the amplified radio signal, the load being disposed between the reference DC voltage and the drain of the second NMOS transistor. The second gate is disposed above a second insulator, the second NMOS transistor has a second transconductance and a second breakdown voltage associated therewith, and the second insulator may be thicker than the first insulator. This results in the first transconductance being greater than the second transconductance, and the second breakdown voltage being greater than the first breakdown voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.