Component and interference suppression circuit
US6850404B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2001 |
| Grant date | Feb 1, 2005 |
| Priority date | — |
| Expiry date | Dec 6, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01G4/30
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An electrical component includes stacked electrode layers arranged on a foundation. The stacked electrode layers include a first type of electrode layer and a second type of electrode layer. Dielectric layers separate the stacked electrode layers to form at least one capacitor. Two pairs of external contacts are arranged such that one external contact in each pair of external contacts is located on a side of the foundation and such that connections between each pair of external contacts overlap. A first pair of the external contacts connects to the first type of electrode layer and a second pair of the external contacts connects to the second type of electrode layer. The first type of electrode layer includes a first conductive layer which connects to at least one of the first pair of external contacts and the second type of electrode layer includes a second conductive layer which connects to at least one of the second pair of external contacts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.