Video signal processing apparatus
US6850694B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2000 |
| Grant date | Feb 1, 2005 |
| Priority date | — |
| Expiry date | Mar 29, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N9/8042
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a video signal processing apparatus for outputting an inputted video signal after subjecting the video signal to time axis correction, particularly to a video signal processing apparatus preferable in the case of subjecting the video signal to image compression. In the case in which a nonstandard signal is inputted to an image compression circuit of an MPEG2 encoder or the like, a drawback of freezing image or generating block noise or the like is resolved. A time axis correcting circuit stores an input signal to a memory and reads the input signal at a timing delayed from V synchronization of the input signal by a predetermined time period. For that purpose, a read synchronizing signal generator is reset at respective input field. A reset position is set to a position preceding the read V synchronization position by 3H through 10H. It is detected whether the input signal is a non-interlace signal or a field length thereof is deviated from a standard value and in these cases, odd/even order or synchronization timing of a synchronizing signal is corrected. Further, when the input signal is a nonstandard signal, the input signal is outputted without p…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.