Method to modify 0.25 μm 1T-RAM by extra resist protect oxide (RPO) blocking
US6852589B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2002 |
| Grant date | Feb 8, 2005 |
| Priority date | — |
| Expiry date | Dec 18, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/09
Abstract
A method to fabricate a 1T-RAM device, comprising the following steps. A semiconductor substrate having an access transistor area and an exposed bottom plate within a capacitor area proximate the access transistor area is provided. A gate with an underlying gate dielectric layer within the access transistor area are formed. The gate and underlying gate dielectric layer having sidewall spacers formed over their respective exposed side walls. A top plate with an underlying capacitor layer over the bottom plate within the capacitor area are formed. The top plate and underlying capacitor layer having sidewall spacers formed over their respective exposed side walls. A patterned resist protect oxide (RPO) layer is formed over at least the drain of the structure not to be silicided. Metal silicide portions are formed over the structure not protected by the RPO layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.