Semiconductor devices with capacitors of metal/insulator/metal structure and methods for forming the same
US6853003B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 1, 2002 |
| Grant date | Feb 8, 2005 |
| Priority date | — |
| Expiry date | Nov 1, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/957
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor devices with copper interconnections and MIM capacitors and methods of fabricating the same are provided. The device includes a lower electrode composed of a first copper layer. A first insulation layer covers a lower electrode. A window is formed in the first insulation layer to expose a portion of the lower electrode. A capacitor includes a lower barrier electrode, a dielectric layer, and an upper barrier electrode, which are sequentially formed to cover a sidewall and a bottom of the window. An intermediate electrode composed of a second copper layer fills a remaining space of an inside of the capacitor. A second insulation layer is formed on the intermediate electrode. A connection hole is formed in the second insulation layer to expose a portion of the intermediate electrode. A connection contact plug composed of a third copper layer fills the connection hole. An upper layer composed of a fourth copper layer is formed on the connection contact plug to be connected to the connection contact plug.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.