Phase-lock loop having programmable bandwidth
US6853252B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 4, 2002 |
| Grant date | Feb 8, 2005 |
| Priority date | — |
| Expiry date | Oct 4, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S331/02
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase-locked loop having a programmable loop bandwidth is provided. A PLL comprises an oscillator operable to receive an error-correction signal and to generate an oscillator signal having a frequency that is related to the error-correction signal. The PLL further comprises a phase-frequency detector (PFD) coupled to the oscillator and operable to receive a reference signal and to generate the error-correction signal based upon a phase difference between the reference signal and a feedback signal derived from the oscillator signal. The PLL further comprises an error-correction signal suppression circuit coupled to the PFD and operable to control the loop bandwidth of the PLL by periodically enabling the PFD.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.