Display device
US6853371B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 2001 |
| Grant date | Feb 8, 2005 |
| Priority date | — |
| Expiry date | Oct 12, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2340/0428
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Within one pixel element 200, two display circuits corresponding to the analog display mode and the digital display mode are disposed such that they are adjacent to each other. One of these two display circuits can be selected through the circuit selection circuits 40 or 43. Since the high voltage power line 150 of the retaining circuit 110, which is used under the digital display mode, also performs as the signal selection line 88, it is possible to have the high density integration of the pixel element 200. Also, the bias voltage Vsc supplied through the selection storage capacitor line 81 is same as the signal A. Therefore, the storage capacitor line 81 is connected to the drain of the TFT 122 of the signal selection circuit 120 so that the signal line 82 for supplying the signal A can be omitted. Thus, the high-density integration of the pixel element 200 can be achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.