Controller for a memory system having multiple partitions
US6853382B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 13, 2000 |
| Grant date | Feb 8, 2005 |
| Priority date | — |
| Expiry date | Feb 21, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/123
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A memory system having a number of partitions each operative to independently service memory requests from a plurality of memory clients while maintaining the appearance to the memory client of a single partition memory subsystem. The memory request specifies a location in the memory system and a transfer size. A partition receives input from an arbiter circuit which, in turn, receives input from a number of client queues for the partition. The arbiter circuit selects a client queue based on a priority policy such as round robin or least recently used or a static or dynamic policy. A router receives a memory request, determines the one or more partitions needed to service the request and stores the request in the client queues for the servicing partitions. In one embodiment, an additional arbiter circuit selects memory requests from one of a subset of the memory clients and forwards the requests to a routing circuit, thereby providing a way for the subset of memory clients to share the client queues and routing circuit. Alternatively, a memory client can make requests directed to a particular partition in which case no routing circuit is required. For a read request that requires m…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.