Methods and apparatuses for a ROM memory array having twisted source or bit lines
US6853572B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 28, 2003 |
| Grant date | Feb 8, 2005 |
| Priority date | — |
| Expiry date | Feb 28, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various methods, apparatuses, and systems in which a read only memory is arrayed in a multiple rows and columns. A first column of memory cells is organized into groups of memory cells including a first group of memory cells and a second group of memory cells. A first source line connects to one or more memory cells in the first group of memory cells. The first source line changes its voltage state during a read operation on one or more bit cells in the first group. A second source line connects to one or more memory cells in the second group of memory cells. The second source line maintains its voltage state during the read operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.