Reducing leakage current in circuits implemented using CMOS transistors
US6853574B2 · kind B2 · utility
4Cited by
6References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 27, 2002 |
| Grant date | Feb 8, 2005 |
| Priority date | — |
| Expiry date | Jul 3, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/811
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Reducing leakage current when a circuit contains a series of CMOS transistors. The probability that each input signal (connecting to the gate terminal of the corresponding CMOS transistor) will be at a logical value which turns off the corresponding CMOS transistor is determined. A CMOS transistor with a high threshold voltage may be connected to receive an input signal with a high probability to reduce the aggregate leakage current in the circuit. The approach may be used in any environments such as synthesis tools and also manual design methodologies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.