Pulse driven single bit line SRAM cell
US6853578B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 2002 |
| Grant date | Feb 8, 2005 |
| Priority date | — |
| Expiry date | Apr 10, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A single bit line, pulse-operated memory cell. The memory cell includes a first and second inverter, write access and feedback-control transistors, and read access transistor and read buffer transistors. The output of the first inverter is connected to the input of the second inverter and the output of the second inverter is connected to the input of the first inverter through the channel of the feedback-control transistor. The write access and feedback-control transistors are opposite types, and their gates are connected together so that when the feedback control transistor is on the write-access transistor is off and visa versa. Writing the cell thus avoids contending the with the on-transistor of the second inverter. The output of the cell is sensed by the gate of the buffer transistor and coupling the output of the buffer transistor through the read access transistor to the read output line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.