Method and apparatus for preventing overtunneling in pFET-based nonvolatile memory cells
US6853583B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2002 |
| Grant date | Feb 8, 2005 |
| Priority date | — |
| Expiry date | Jan 1, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3472
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatuses prevent overtunneling in pFET-based nonvolatile floating gate memory (NVM) cells. During a tunneling process, in which charge carriers are removed from a floating gate of a pFET-based NVM cell, a channel current of a memory cell transistor is monitored and compared to a predetermined minimum channel current required to maintain a conducting channel in an injection transistor of the memory cell. When the monitored channel current drops below the predetermined minimum channel current, charge carriers are injected onto the floating gate by impact-ionized hot-electron injection (IHEI) so that overtunneling is avoided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.