Semiconductor memory device
US6853595B2 · kind B2 · utility
9Cited by
11References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2002 |
| Grant date | Feb 8, 2005 |
| Priority date | — |
| Expiry date | Aug 29, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device having a plurality of pair cells including a pair of cells for storing ordinary data and auxiliary data in which the operation of one cell in a pair cell can be checked. At normal operation time data can be read from or written to a desired cell by activating two word lines at a time. On the other hand, at operation test time data can be read from or written to only one cell in a pair cell by activating a desired word line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.