Efficient interpolator for high speed timing recovery
US6854002B2 · kind B2 · utility
26Cited by
15References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 16, 2003 |
| Grant date | Feb 8, 2005 |
| Priority date | — |
| Expiry date | May 16, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B20/1403
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A data processing circuit includes a digital data source having an output carrying a sequence of digital signals. A pre-filter is coupled to the output of the digital data source. The pre-filter has a first output that carries a second sequence of digital signals and a second output that carries a third sequence of digital signals. The second sequence of digital signals is time shifted relative to the third sequence of digital signals. The circuit also includes an interpolation circuit with a first input coupled to the first output of the pre-filter and a second input coupled to the second output of the pre-filter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.