Reducing variation in randomized nanoscale circuit connections
US6854092B2 · kind B2 · utility
12Cited by
5References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 12, 2002 |
| Grant date | Feb 8, 2005 |
| Priority date | — |
| Expiry date | Mar 11, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/936
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A method and apparatus of reducing variations in nanoscale circuit connections. One exemplary embodiment includes: placing a first connector between a first addressing wire and a first nanowire in a partial circuit; and applying bias to the partial circuit so that a second connector is placed between a second addressing wire and a second nanowire. This method of bias connections is repeated for each wire in the full circuit. Thus, bias is used to influence the positioning of connectors on additional wires (if any) in the full circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.