Apparatus and method for visualizing and analyzing resistance networks
US6854103B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 30, 2002 |
| Grant date | Feb 8, 2005 |
| Priority date | — |
| Expiry date | Mar 7, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for automatically generating a visual representation of a resistance network and an equivalent point to point resistance for any set of terminals on the resistance network are provided. With the apparatus and method, a cell layout is input to a resistance/capacitance (RC) extraction tool. The RC extraction tool extracts the RC parasitics from the cell layout and inputs them into a resistance network visualization and analysis tool. From the RC parasitics, a graph data structure representation of the resistance network is generated. The graph data structure of the resistance network may then be reduced using, for example, a single layer series and parallel reduction, all layers series and parallel reduction, layer specific reduction, or the like. Following reduction, if any, a visual representation of the resistance network is generated using the graph data structure. Thereafter, equivalent point to point resistance for any set of terminals on the resistance network may be generated. The point to point resistance may be used for detailed analysis and verification of the extracted parasitics. The equivalent resistance is calculated using mesh and matrix analys…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.