Method for fabricating a high-voltage high-power integrated circuit device
US6855581B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 23, 2002 |
| Grant date | Feb 15, 2005 |
| Priority date | — |
| Expiry date | Jun 10, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/01
Abstract
The present invention relates to a method of fabricating a high-voltage high-power integrated circuit device using a substrate of a SOI structure in which an insulating film and a silicon layer are sequentially stacked on a silicon substrate. The method comprising the steps of sequentially forming an oxide film and a photoresist film on the silicon layer and then performing a photolithography process using a trench mask to pattern the photoresist film; patterning the oxide film using the patterned photoresist film as a mask and then removing the photoresist film remained after the patterning; etching the silicon layer using the patterned oxide film as a mask until the insulating film is exposed to form a trench; forming a nitride film on the entire surface including the trench, performing an annealing process and depositing polysilicon on the entire surface so that the trench is buried; and sequentially removing the polysilicon and the nitride film until the silicon layer is exposed to flatten the surface, thus forming a device isolating film for electrical isolation between devices within the trench. Therefore, the present invention can effectively reduce the isolation area of the…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.