CMOS buffer with reduced ground bounce
US6856179B2 · kind B2 · utility
4Cited by
13References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2003 |
| Grant date | Feb 15, 2005 |
| Priority date | — |
| Expiry date | Sep 12, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/166
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A CMOS output buffer uses feedback from a ground node to reduce ground bounce by utilizing a tolerable ground bounce limit, making it less sensitive to operating conditions and processing parameters. An input to the NMOS device of the output buffer is provided by the output of a control element which receives a first input from a pre-driver and a second input (i.e., the feedback) from the ground node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.