Digital PLL circuit operable in short burst interval
US6856658B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2000 |
| Grant date | Feb 15, 2005 |
| Priority date | — |
| Expiry date | Apr 26, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0083
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital PLL (phase locked loop) circuit includes a sampling circuit, a plurality of internal circuits and an output switching circuit. The sampling circuit samples a burst data signal in response to a multi-phase clock signal to produce N (N is a positive integer larger than one) sampled data signals. The multi-phase clock signal includes N clock signals, each of which has substantially the same frequency as the data signal and which have phases different by a predetermined component from one after another. Each of the plurality of internal circuits is selected in response to a first selection signal, and outputs a set of a selected one of the N clock signals and an identified data signal from the N sampled data signals, which corresponds to the selected clock signal, in response to the selected clock signal, when the internal circuit is selected. The output switching circuit selects the set corresponding to the selected internal circuit from among the sets from the plurality of internal circuits based on a second selection signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.