High linearity circuits and methods regarding same
US6856796B2 · kind B2 · utility
11Cited by
13References
75Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2002 |
| Grant date | Feb 15, 2005 |
| Priority date | — |
| Expiry date | May 31, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/453
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Circuits and methods that improve linearity with use of cancellation of at least a portion, and preferably, substantially all of, at least one significant harmonic from the output of a primary circuit, e.g., the 3rd harmonic, using the output of a substantially functionally identical auxiliary circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.