System, apparatus and method for prioritizing instructions and eliminating useless instructions
US6857060B2 · kind B2 · utility
23Cited by
14References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2001 |
| Grant date | Feb 15, 2005 |
| Priority date | — |
| Expiry date | Dec 30, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3858
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a method features operations for executing instructions in an instruction window. The first and second instructions are examined to determine their sources and destinations. The written on bit of the first instruction is set to a “written on” state if the destinations of the first and second instructions are the same while a used bit of the first instruction is set to a “used” state if the source of the second instruction is the destination of the first instruction. Thereafter, a priority of the first instruction can be determined from the written on and used bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.