Multiprocessor system and method for simultaneously placing all processors into debug mode
US6857084B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 6, 2001 |
| Grant date | Feb 15, 2005 |
| Priority date | — |
| Expiry date | Mar 6, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3648
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Multiple processors of a multiprocessor system are placed into a debug mode of operation approximately simultaneously when one processor initially enters the debug mode as a result of incurring a debug event. The other processors enter the debug mode as a result of the one processor asserting a debug event signal upon initially entering the debug mode. A logic circuit associated with each processor responds to any debug event signal asserted by another processor and the failure of its associated processor to assert a debug event signal, to assert an external debug break signal to the associated processor and place the associated processor into the debug mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.