Hierarchy of fault isolation timers
US6857086B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 21, 2003 |
| Grant date | Feb 15, 2005 |
| Priority date | — |
| Expiry date | Apr 21, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0793
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In the present invention, a coordinated hierarchy of timing mechanisms preferably cooperate to report errors at different operational levels of a complex of computing devices. Preferably, each timer is able to identify a failure condition at its own level of operation and transmit a time-out condition to a higher level device which may also be a timer. Upon generation of a time-out condition, a system component experiencing a fault condition preferably continues to operate in a degraded mode, informs devices attempting to communicate with the faulty component of a status of the fault condition, and preferably proceeds to identify and correct a failure which caused the time out condition. The timers may be implemented in hardware or software.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.