System and method for automatically analyzing and managing loss factors in test process of semiconductor integrated circuit devices
US6857090B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 9, 2001 |
| Grant date | Feb 15, 2005 |
| Priority date | — |
| Expiry date | May 24, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5606
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system and method automatically analyzes and manages loss factor data of test processes in which a great number of IC devices are tested as a lot with a number of testers. The lot contains a predetermined number of identical IC devices, and the lot test process is performed sequentially according to a predetermined number of test cycles. The system include a means for verifying test results for each of the test cycles and for determining whether or not a re-test is to be performed and an IC device loading/unloading means for loading IC devices to be tested and contained in the lot to a test head and for unloading the tested IC devices from the test head by sorting the tested IC devices according to the test results. The system also includes raw data generating means for generating raw data on the basis of time data occurring when the test process is performed; data calculating means for calculating testing time data, index time data based on the raw data, and loss time data; data storage means for storing the raw data and the calculated data; and data analyzing and outputting means for analyzing the raw data and the calculated data according to the lots, the plurality of testers …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.