Stacked chip package with heat transfer wires
US6857470B2 · kind B2 · utility
23Cited by
11References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2003 |
| Grant date | Feb 22, 2005 |
| Priority date | — |
| Expiry date | Nov 20, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a stacked chip package having at least one heat transfer wire. The heat transfer wire is disposed between the stacked chips and at least one end of each transfer wire is connected to a dummy pad provided on the board. Therefore, the heat generated by the chips and trapped between the chips can be effectively dissipated. The heat transfer wires can be formed on the uppermost chip of the stacked chips to enhance the heat dissipation. In addition, by controlling the number or the size of the heat transfer wire, the thermal characteristics of the stacked chip package can be modified.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.