BJT device configuration and fabrication method with reduced emitter width
US6858887B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2003 |
| Grant date | Feb 22, 2005 |
| Priority date | — |
| Expiry date | Jul 30, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/85
Abstract
A BJT device configuration includes an emitter finger and via arrangement which reduces emitter finger width, and is particularly suitable for use with compound semiconductor-based devices. Each emitter finger includes a cross-shaped metal contact which provides an emitter contact; each contact comprises two perpendicular arms which intersect at a central area. A via through an interlevel dielectric layer provides access to the emitter contact; the via is square-shaped, centered over the center point of the central area, and oriented at a 45° angle to the arms. This allows the via size to be equal to or greater than the minimum process dimension, while allowing the width of the emitter finger to be as narrow as possible with the alignment tolerances still being met.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.