Individually adjustable back-bias technique
US6858897B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 30, 2003 |
| Grant date | Feb 22, 2005 |
| Priority date | — |
| Expiry date | Apr 30, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
An individual-well adaptive method of body bias control that mitigates the effects of D2D and WD process variations is shown. It is assumed that p-type transistors are grouped in sections. The bodies of all the p-type transistors within a section are connected to a single n-well. This section size can be small enough to provide fine-granular adjustments to the circuit without having any impact on area overhead. With a small amount of additional circuitry and routing, individual well biases can be intelligently adjusted resulting in closely controlled chip power and performance. Experimental results show that binning yields as low as 17% can be improved to greater than 90% using the proposed method.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.