Patent · US Expired

Design-for-test modes for a phase locked loop

US6859028B2 · kind B2 · utility

29Cited by
3References
16Claims
0Family size

Assignee

Inventor

Key dates

Filing dateNov 26, 2002
Grant dateFeb 22, 2005
Priority date—
Expiry dateApr 19, 2023

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG01R31/2884
  • WIPO fieldMeasurement
  • WIPO sectorInstruments

Abstract

There is a desire to provide a testing method and apparatus that can be successfully integrated into a PLL and PLL-like circuits (e.g. frequency synthesizers, delay lock loops, etc.). It is desirable that the PLL or PLL-like circuit integrated with testing apparatus does not suffer from performance degradations during nominal (mission mode) operation. Furthermore, it is desirable that the PLL and the testing apparatus share the same interface. In order to produce a PLL having integrated testing apparatus, without having the PLL suffer severe performance degradations during nominal operation nor having the combination of the PLL and testing apparatus be unnecessarily large, a modified PLL integrated with testing apparatus is provided.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.