Frequency comparator with hysteresis between locked and unlocked conditions
US6859107B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2003 |
| Grant date | Feb 22, 2005 |
| Priority date | — |
| Expiry date | Feb 13, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S331/02
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A frequency comparator apparatus used with a reference clock, a voltage controlled oscillator circuit and a phase locked loop circuit includes a reference loop circuit wherein the reference loop circuit is activated when the frequency difference between the reference clock and the voltage controlled oscillator circuit is greater than about a first threshold. Also included is a data loop circuit wherein the data loop circuit is activated when the frequency difference between the reference clock and the voltage controlled oscillator circuit is less than about a second threshold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.