Signal detection circuit for detecting multiple match in arranged signal lines
US6859376B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2003 |
| Grant date | Feb 22, 2005 |
| Priority date | — |
| Expiry date | Feb 25, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A signal detection circuit detects the presence or absence of signals having the same logic in a plurality of arranged signal lines, can be used as a circuit suitable for multi-hit detection in a content addressable memory. The signal detection circuit includes a first signal transmission line to transmit a first signal indicating the presence of two or more logical signals to be detected and a second signal transmission line to transmit a second signal indicating the presence of one or more of the logic signals to be detected. Each of the first and second signal transmission lines includes logic circuits. The signal detection circuit may have a hierarchical structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.