Multiple match detection logic and gates for content addressable memory (CAM) devices
US6859378B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 2004 |
| Grant date | Feb 22, 2005 |
| Priority date | — |
| Expiry date | Jun 16, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Content addressable memory (CAM) devices according to embodiments of the present invention include high performance multiple match detection circuits therein. These match detection circuits use 2-to-1 multiple match gates that are small, consume no static power and are hierarchically cascadable. The match detection circuits are also configured so that match signal inputs see small fanouts and high speed operation can be achieved. At each intermediate and final stage of the match detection circuit, the multiple match gates process two pairs of inputs into a single pair of outputs. In particular, a match detection circuit is configured to generate a final multiple match flag (MMF) and a final any match flag (AMF) in response to input match signals, with the match detection circuit including log2N stages of 2-to-1 multiple match gates, where N=2k and k is a positive integer. The final MMF is set to an active level whenever at least two of the input match signals indicate a match condition and the AMF is set to an active level whenever at least one of the input match signals indicates a match condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.