Three-state binary adders and methods of operating the same
US6859387B1 · kind B1 · utility
3Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 12, 2000 |
| Grant date | Feb 22, 2005 |
| Priority date | — |
| Expiry date | May 12, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/44
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Three-state binary adders are disclosed for use in pipelined analog-to-digital converters. According to one advantageous embodiment, a three-state binary adder is provided for use in a digital signal processing system. The three-state binary adder is operable to generate binary codes consisting of three states, namely, “00”, “01” and “10.”
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.