EEPROM architecture and programming protocol
US6859391B1 · kind B1 · utility
9Cited by
10References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2003 |
| Grant date | Feb 22, 2005 |
| Priority date | — |
| Expiry date | Jan 30, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An EEPROM memory circuit in which the loading of the column latches can be performed simultaneously with reading of the memory array. In this memory circuit, the data input connects directly to the column latches, leaving the bit lines open for memory reading by the sense amplifiers, which is connected directly to the bit lines. Two separate Y address decoders, one feeding into the column latches and the other into the bit line select circuit, provide column latch and bit line selection respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.