Parallel decimation circuits
US6859813B2 · kind B2 · utility
2Cited by
2References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2001 |
| Grant date | Feb 22, 2005 |
| Priority date | — |
| Expiry date | Aug 8, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/17
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A decimation system and decimation circuit for decimating waveform data on an oscilloscope. The decimation circuit is implemented using sixteen parallel 16-to-1 multiplexers connected in parallel to a data bus which selectively captures samples based on control signals generated by a sample counting circuit. Decimation factor and phase values can be input to program the amount of decimation performed by the circuit. The decimation system provides even more flexibility in controlling the decimation and is formed by combining several of the decimation circuits with corresponding analog-to-digital converters and memory segments.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.