Circuit for controlling sequential access to SDRAM
US6859848B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 2003 |
| Grant date | Feb 22, 2005 |
| Priority date | — |
| Expiry date | Apr 17, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A DMA controller arbitrates and selects a DMA control information signal received from at least one of a plurality of DMA request blocks and accesses an SDRAM on the basis of the selected DMA control information signal. In the DMA controller, an SDRAM controller detects using a detector the number of possible sequential accesses on the basis of a DMA start address signal, compares using a comparator this number of possible sequential accesses with the burst DMA request number designated by a BSTNUM signal, selects not larger one of the two numbers, and sets the number of sequential DMAs to be actually executed to the selected number. Accordingly, with a simple configuration, sequential access is made possible starting from an arbitrary address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.