Parallel data communication consuming low power
US6859883B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2001 |
| Grant date | Feb 22, 2005 |
| Priority date | — |
| Expiry date | Dec 23, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one example embodiment involving a high-speed parallel-data communication from a first module to a second module, a termination circuit is adapted to reduce power consumption at the second module. The termination circuit includes resistive circuits respectively coupled to a plurality of parallel data-carrying lines that form the data bus. The other ends of the resistive circuits are interconnected to provide a reference voltage using the data on the parallel data-carrying lines. Consistent with one embodiment of the present invention, the communication approach uses data sets encoded so that each data set includes the same number of ones and zeroes; in this manner the reference voltage is always at midpoint and useful in providing termination to the data-carrying lines at all times.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.